On-Chip Training NPU - Algorithm, Architecture and SoC Design
Unlike most available sources that focus on deep neural network (DNN) inference, this book provides readers with a single-source reference on the needs, requirements, and challenges involved with on-device, DNN training semiconductor and SoC design. The authors include coverage of the trends and his...
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| Príomhchruthaitheoirí: | , |
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| Údar corparáideach: | |
| Formáid: | Leictreonach Ríomhleabhar |
| Teanga: | Béarla |
| Foilsithe / Cruthaithe: |
Cham :
Springer Nature Switzerland : Imprint: Springer,
2023.
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| Eagrán: | 1st ed. 2023. |
| Ábhair: | |
| Rochtain ar líne: | https://doi.org/10.1007/978-3-031-34237-0 |
| Clibeanna: |
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| Achoimre: | Unlike most available sources that focus on deep neural network (DNN) inference, this book provides readers with a single-source reference on the needs, requirements, and challenges involved with on-device, DNN training semiconductor and SoC design. The authors include coverage of the trends and history surrounding the development of on-device DNN training, as well as on-device training semiconductors and SoC design examples to facilitate understanding. Focuses on the requirements and challenges of on-device deep neural network (DNN) training, rather than DNN inference; Provides guidelines for on-device, DNN training semiconductor or System-on-Chip (SoC) design; Includes on-device training semiconductors and SoC design examples to facilitate understanding. |
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| Cur síos fisiciúil: | 1 online resource (XXIII, 237 p. 234 illus.). 213 illus. in color. |
| ISBN: | 9783031342370 |
| DOI: | 10.1007/978-3-031-34237-0 |