On-Chip Training NPU - Algorithm, Architecture and SoC Design
Unlike most available sources that focus on deep neural network (DNN) inference, this book provides readers with a single-source reference on the needs, requirements, and challenges involved with on-device, DNN training semiconductor and SoC design. The authors include coverage of the trends and his...
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| Autors principals: | , |
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| Autor corporatiu: | |
| Format: | Electrònic eBook |
| Idioma: | anglès |
| Publicat: |
Cham :
Springer Nature Switzerland : Imprint: Springer,
2023.
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| Edició: | 1st ed. 2023. |
| Matèries: | |
| Accés en línia: | https://doi.org/10.1007/978-3-031-34237-0 |
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| 100 | 1 | |a Han, Donghyeon. |e author. |0 (orcid)0000-0002-5212-2072 |1 https://orcid.org/0000-0002-5212-2072 |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 245 | 1 | 0 | |a On-Chip Training NPU - Algorithm, Architecture and SoC Design |h [electronic resource] / |c by Donghyeon Han, Hoi-Jun Yoo. |
| 250 | |a 1st ed. 2023. | ||
| 264 | 1 | |a Cham : |b Springer Nature Switzerland : |b Imprint: Springer, |c 2023. | |
| 300 | |a 1 online resource (XXIII, 237 p. 234 illus.). |b 213 illus. in color. | ||
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| 505 | 0 | |a Chapter 1 Introduction -- Chapter 2 A Theoretical Study on Artificial Intelligence Training -- Chapter 3 New Algorithm 1: Binary Direct Feedback Alignment for Fully-Connected layer -- Chapter 4 New Algorithm 2: Extension of Direct Feedback Alignment to Convolutional Recurrent Neural Network -- Chapter 5 DF-LNPU: A Pipelined Direct Feedback Alignment based Deep Neural Network Learning Processor for Fast Online Learning -- Chapter 6 HNPU-V1: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-point and Active Bit-precision Searching -- Chapter 7 HNPU-V2: An Energy-efficient DNN Training Processor for Robust Object Detection with Real-World Environmental Adaptation -- Chapter 8 An Overview of Energy-efficient DNN Training Processors -- Chapter 9 Conclusion. | |
| 520 | |a Unlike most available sources that focus on deep neural network (DNN) inference, this book provides readers with a single-source reference on the needs, requirements, and challenges involved with on-device, DNN training semiconductor and SoC design. The authors include coverage of the trends and history surrounding the development of on-device DNN training, as well as on-device training semiconductors and SoC design examples to facilitate understanding. Focuses on the requirements and challenges of on-device deep neural network (DNN) training, rather than DNN inference; Provides guidelines for on-device, DNN training semiconductor or System-on-Chip (SoC) design; Includes on-device training semiconductors and SoC design examples to facilitate understanding. | ||
| 532 | 8 | |a Accessibility summary: This PDF does not fully comply with PDF/UA standards, but does feature limited screen reader support, described non-text content (images, graphs), bookmarks for easy navigation and searchable, selectable text. Users of assistive technologies may experience difficulty navigating or interpreting content in this document. We recognize the importance of accessibility, and we welcome queries about accessibility for any of our products. If you have a question or an access need, please get in touch with us at accessibilitysupport@springernature.com. | |
| 532 | 8 | |a No reading system accessibility options actively disabled | |
| 532 | 8 | |a Publisher contact for further accessibility information: accessibilitysupport@springernature.com | |
| 588 | |a Print version record. | ||
| 650 | 0 | |a Electronic circuits. | |
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| 650 | 2 | 4 | |a Processor Architectures. |
| 700 | 1 | |a Yoo, Hoi-Jun. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
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