On-Chip Training NPU - Algorithm, Architecture and SoC Design

Unlike most available sources that focus on deep neural network (DNN) inference, this book provides readers with a single-source reference on the needs, requirements, and challenges involved with on-device, DNN training semiconductor and SoC design. The authors include coverage of the trends and his...

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Αποθηκεύτηκε σε:

Λεπτομέρειες βιβλιογραφικής εγγραφής
Κύριοι συγγραφείς:	Han, Donghyeon (Συγγραφέας), Yoo, Hoi-Jun (Συγγραφέας)
Συγγραφή απο Οργανισμό/Αρχή:	SpringerLink (Online service)
Μορφή:	Ηλεκτρονική πηγή Ηλ. βιβλίο
Γλώσσα:	Αγγλικά
Έκδοση:	Cham : Springer Nature Switzerland : Imprint: Springer, 2023.
Έκδοση:	1st ed. 2023.
Θέματα:	Electronic circuits. Embedded computer systems. Microprocessors. Computer architecture. Electronic Circuits and Systems. Embedded Systems. Processor Architectures.
Διαθέσιμο Online:	https://doi.org/10.1007/978-3-031-34237-0
Ετικέτες:	Προσθήκη ετικέτας Δεν υπάρχουν, Καταχωρήστε ετικέτα πρώτοι!

Πίνακας περιεχομένων:

Chapter 1 Introduction
Chapter 2 A Theoretical Study on Artificial Intelligence Training
Chapter 3 New Algorithm 1: Binary Direct Feedback Alignment for Fully-Connected layer
Chapter 4 New Algorithm 2: Extension of Direct Feedback Alignment to Convolutional Recurrent Neural Network
Chapter 5 DF-LNPU: A Pipelined Direct Feedback Alignment based Deep Neural Network Learning Processor for Fast Online Learning
Chapter 6 HNPU-V1: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-point and Active Bit-precision Searching
Chapter 7 HNPU-V2: An Energy-efficient DNN Training Processor for Robust Object Detection with Real-World Environmental Adaptation
Chapter 8 An Overview of Energy-efficient DNN Training Processors
Chapter 9 Conclusion.

On-Chip Training NPU - Algorithm, Architecture and SoC Design

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