Versatile Hardware Analysis Techniques From Waveform-based Analysis to Formal Verification /

This book describes several versatile hardware analysis techniques that tackle existing and new challenges. These techniques cover different phases of the hardware development process, including the verification, debugging, and post-synthesis optimization phases. The authors introduce the Waveform A...

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Váldodahkkit: Klemmer, Lucas (Dahkki), Große, Daniel (Dahkki)
Searvvušdahkki: SpringerLink (Online service)
Materiálatiipa: Elektrovnnalaš E-girji
Giella:eaŋgalasgiella
Almmustuhtton: Cham : Springer Nature Switzerland : Imprint: Springer, 2025.
Preanttus:1st ed. 2025.
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Liŋkkat:https://doi.org/10.1007/978-3-031-83093-8
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LEADER 00000nam a22000005i 4500
001 978-3-031-83093-8
003 DE-He213
005 20260706115752.0
007 cr nn 008mamaa
008 250307s2025 sz | s |||| 0|eng d
020 |a 9783031830938  |9 978-3-031-83093-8 
024 7 |a 10.1007/978-3-031-83093-8  |2 doi 
050 4 |a TK7867-7867.5 
072 7 |a TJFC  |2 bicssc 
072 7 |a TEC008010  |2 bisacsh 
072 7 |a TJFC  |2 thema 
082 0 4 |a 621.3815  |2 23 
100 1 |a Klemmer, Lucas.  |e author.  |4 aut  |4 http://id.loc.gov/vocabulary/relators/aut 
245 1 0 |a Versatile Hardware Analysis Techniques  |h [electronic resource] :  |b From Waveform-based Analysis to Formal Verification /  |c by Lucas Klemmer, Daniel Große. 
250 |a 1st ed. 2025. 
264 1 |a Cham :  |b Springer Nature Switzerland :  |b Imprint: Springer,  |c 2025. 
300 |a XVI, 190 p. 38 illus., 25 illus. in color.  |b online resource. 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
341 0 |b Table of contents navigation  |2 onix 
341 0 |b Single logical reading order  |2 onix 
341 0 |b Short alternative textual descriptions  |2 onix 
341 0 |b Use of color is not sole means of conveying information  |2 onix 
341 0 |b Use of high contrast between text and background color  |2 onix 
341 0 |b Next / Previous structural navigation  |2 onix 
341 0 |b All non-decorative content supports reading without sight  |2 onix 
347 |a text file  |b PDF  |2 rda 
505 0 |a Chapter 1 Introduction -- Chapter 2 Background -- Chapter 3 Processor Verification by Equivalent Program Execution -- Chapter 4 A Formally Verified Microcoded RISC-V Platform -- Chapter 5 The Waveform Analysis Language -- Chapter 6 Programmable Analysis of RISC-V Processors using WAL -- Chapter 7 HDL-Integrated Waveform Analysis -- Chapter 8 An Interactive Debugging Methodology Based on WAL -- Chapter 9 Netlist Optimization using Formal Methods under ExternalConstraints -- Chapter 10 Conclusion and Outlook. 
520 |a This book describes several versatile hardware analysis techniques that tackle existing and new challenges. These techniques cover different phases of the hardware development process, including the verification, debugging, and post-synthesis optimization phases. The authors introduce the Waveform Analysis Language (WAL), which allows users to code analysis tasks in the form of programs that run on waveforms. The book covers processor verification, formal microcode verification, programmable automated waveform analysis demonstrated for a large variety of previously manual analysis tasks, as well as netlist optimization leveraging formal methods. All methods are available as open source, typically include examples on RISC-V analysis problems, providing a strong foundation for the community. Introduces automated waveform analysis based on a DSL to execute programs on waveforms; Includes practical examples for waveform analysis including demonstrations for RISC-V processors; Presents novel approaches for processor verification, microcode verification and netlist optimization with formal methods. 
532 8 |a Accessibility summary: This PDF does not fully comply with PDF/UA standards, but does feature limited screen reader support, described non-text content (images, graphs), bookmarks for easy navigation and searchable, selectable text. Users of assistive technologies may experience difficulty navigating or interpreting content in this document. We recognize the importance of accessibility, and we welcome queries about accessibility for any of our products. If you have a question or an access need, please get in touch with us at accessibilitysupport@springernature.com. 
532 8 |a No reading system accessibility options actively disabled 
532 8 |a Publisher contact for further accessibility information: accessibilitysupport@springernature.com 
650 0 |a Electronic circuit design. 
650 0 |a Embedded computer systems. 
650 0 |a Logic design. 
650 1 4 |a Electronics Design and Verification. 
650 2 4 |a Embedded Systems. 
650 2 4 |a Logic Design. 
700 1 |a Große, Daniel.  |e author.  |0 (orcid)0000-0002-1490-6175  |1 https://orcid.org/0000-0002-1490-6175  |4 aut  |4 http://id.loc.gov/vocabulary/relators/aut 
710 2 |a SpringerLink (Online service) 
773 0 |t Springer Nature eBook 
776 0 8 |i Printed edition:  |z 9783031830921 
776 0 8 |i Printed edition:  |z 9783031830945 
776 0 8 |i Printed edition:  |z 9783031830952 
856 4 0 |u https://doi.org/10.1007/978-3-031-83093-8 
912 |a ZDB-2-ENG 
912 |a ZDB-2-SXE 
912 |a ZDB-2-233 
950 |a Engineering (SpringerNature-11647) 
950 |a Engineering (R0) (SpringerNature-43712) 
950 |a Focus Bundle Electrical and Electronic Engineering (SpringerNature-85403)