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Applied Reconfigurable Computing. Architectures, Tools, and Applications 21st International Symposium, ARC 2025, Seville, Spain, April 9–11, 2025, Proceedings /

This book constitutes the proceedings of the 21st International Symposium on Applied Reconfigurable Computing. Architectures, Tools, and Applications, ARC 2025, held in Seville, Spain, during April 9–11, 2025. The 12 full papers presented in this book together with 1 short paper from the technical p...

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Autor corporatiu: SpringerLink (Online service)
Altres autors: Giorgi, Roberto (Editor), Stojilović, Mirjana (Editor), Stroobandt, Dirk (Editor), Brox Jiménez, Piedad (Editor), Barriga Barros, Ángel (Editor)
Format: Electrònic eBook
Idioma:anglès
Publicat: Cham : Springer Nature Switzerland : Imprint: Springer, 2025.
Edició:1st ed. 2025.
Col·lecció:Lecture Notes in Computer Science, 15594
Matèries:
Computers.
Computer engineering.
Computer networks .
Software engineering.
Computer Hardware.
Computer Engineering and Networks.
Software Engineering.
Accés en línia:https://doi.org/10.1007/978-3-031-87995-1
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Taula de continguts:
  • First Twenty Years of the International Symposium on Applied Reconfigurable Computing (ARC): a Selection of Papers
  • HT-NoC: Reconfigurable High Throughput Network-on-Chip for AI Dataflow Accelerators
  • An MLIR-based Compilation Framework for CGRA Application Deployment
  • Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA
  • RePAIR: Reconfigurable Platform for AI Resilience within RISC-V Ecosystem
  • ROBoost: A Study of FPGA Logic-Based Power-Wasting Primitives
  • FLARE: An FPGA-based Universal Large Flow Detection Engine
  • Out-of-the-Box Performance of FPGAs for ML Workloads using Vitis AI
  • A Heterogeneous Embedded Platform for AI-based Protocol Identification
  • Counting Heavy Items in Filtered Data Streams Using an HLS-Generated FPGA Kernel
  • Ultra-low Latency and Extreme Throughput Echo State Neural Networks on FPGA
  • A Reconfigurable Stream-Based FPGA Accelerator for Bayesian Confidence Propagation Neural Networks
  • Real-Time Multi-Object Tracking using YOLOv8 and SORT on a SoC FPGA
  • Dynamic Function Exchange in FPGA to Redefine RISC-V Multicore Architectures at Runtime.

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