Accelerating Network Functions Using Reconfigurable Hardware Design and Validation of High Throughput and Low Latency Network Functions at the Access Edge /
This book reports on new concepts and methods to design network functions on programmable hardware to accelerate connectivity. First, it introduces the host bypassing concept for improved integration of hardware accelerators in computer systems operating 5G radio access networks. This novel concept...
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| Natura: | Elettronico eBook |
| Lingua: | inglese |
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Cham :
Springer Nature Switzerland : Imprint: Springer,
2024.
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| Edizione: | 1st ed. 2024. |
| Serie: | Springer Theses, Recognizing Outstanding Ph.D. Research,
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| Accesso online: | https://doi.org/10.1007/978-3-031-52872-9 |
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Sommario:
- Introduction
- Background and State-of-the Art
- Design of QOS-Aware Network Functions
- P4sta: High precision network Function Benchmarking
- Evaluation.